1. Field of the Invention
The present invention relates to nonvolatile memory devices and more particularly, to a NAND flash memory device sharing source selection transistors to which a voltage is applied through a source selection line for dual-memory block.
2. Discussion of Related Art
NAND flash memory devices, as electrically erasable and programmable nonvolatile memory devices, are widely used in portable computers, personal digital assistants, mobile phones such as cellular phones, computer BIOS chips, printers, universal serial buses, and so on. A memory cell of the flash memory device is electrically programmable and erasable with a thin oxide film (hereinafter, referred to as “tunnel oxide film”) about 100 Å in thickness, in which electrons move by a strong electric field and a threshold voltage varies to initiate programming and erasing functions.
FIG. 1A is a circuit diagram of a conventional NAND flash memory device, and FIG. 1B shows voltage conditions during programming and reading operations in the NAND flash memory device of FIG. 1A.
Referring to FIG. 1A, in a memory block, both ends of a memory cell are connected to a drain selection transistor DST supplied with a voltage through a single drain selection line DSL, and a source selection transistor SST supplied with a voltage through a single source selection line SSL. The source selection transistor SST is also coupled to a common source line CSL.
Hereinafter, it will be described about the voltage conditions of the programming and reading operations with reference to FIGS. 1A and 1B.
A selected bitline BL1 to be programmed is set to 0V, as shown in FIG. 1B, while a gate of the drain selection transistor DST is set to a power source voltage VCC through the drain selection line DSL. Then, a channel of a memory cell coupled to the bitline BL1 to be programmed is kept open and maintained at 0V. In this condition, if a program voltage Vpgm is applied to a memory cell through a selected wordline WL, the tunnel oxide film of the selected memory cell is charged with a high voltage to conduct the programming operation.
However, as a deselected bitline BL2 not to be programmed is coupled to the power source voltage VCC with the same drain selection transistor DST, the channel voltage of deselected bitline BL2 increases because the drain selection transistor DST is turned on when the channel voltage of the memory cell rises over VCC−Vt (Vt is a threshold voltage of the drain selection transistor DST). Thus, a memory connected to the wordline of the memory cell to be programmed is not programmed because the voltage applied to the tunnel oxide film decreases due to the channel voltage elevation.
In the reading operation, a voltage of 4.5V is applied to the gate of the drain selection transistor DST through the drain selection line DSL, and the voltage of 4.5 V is also applied to a gate of the source selection transistor SST through the source selection line SSL. The common source line CSL is supplied with 0V. 1V is applied to a bitline selected for the reading operation, while 0V is applied to a deselected bitline. Then, the drain selection transistor DST and the source selection transistor SST are kept on to make current flow depending on a read condition of the selected memory cell. 0V is applied to BULK during the programming and reading operations.
As stated above, since the single block has the drain selection transistors DST supplied with a voltage through the single drain selection line DSL, the source selection transistors SST supplied with the single source selection line SSL, and the source selection transistors SST are coupled to the common source line CSL, the chip size of the flash memory device may become increasingly large.